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THC63LVD1022_rev.1.02_e copyright?2013 thin e electronics, inc. 1 thine electronics, inc. THC63LVD1022 30bit color/150mpps dual-link lvds to lvcmos converter general description the THC63LVD1022 lvds (low voltage differential signaling) converter is designed to support pixel data transmission between host and flat panel display up to full-hd 1080p resolutions. the THC63LVD1022 receives dual channel lvds data stream and transm its l vttl/lvcmos data through dual pixel link input / single link output conversion. at a transmit data of 150mpixel/sec, 30bits/pixel and 5bits of timing and con trol data (hsync, vsync, de) are received at an effective rate of 525mbps per lvds channel. application ? security camera / industrial camera ? medium and small size panel ? tablet pc / notebook pc ? multi function printer ? industrial equipment ? medical equipment monitor features ? 20mhz to 75mhz 30bits/pixel dual-link lvds input ? up to 150mhz 30bit s/pixel single port lvcmos output ? operating temperature range : 0 to 85 c ? lvds input skew margin: 400ps at 75mhz ? dual input / single output mode [clkout = 2x clkin] ? output enable / disable mode supported ? no special start-up sequence required ? 100pin tqfp package ? 3.3v single voltage power supply. ? pll requires no external components. ? environmental laws and regulations compliance (ex. eu rohs) block diagram figure 1. block diagram
pin diagram THC63LVD1022 22 23 18 19 20 21 14 15 16 17 10 11 12 13 24 1 2 3 4 5 6 7 8 9 25 re2- rd2+ rd2- rclk2+ ra1- ra1+ rclk2- rc2+ rc2- rb2+ rb2- ra2+ ra2- gnd re1+ re1- rd1+ rd1- rclk1+ rb1+ rc1- rclk1- rc1+ rb1- re2+ 97 98 99 100 93 94 95 96 89 90 91 92 85 86 87 88 81 82 83 84 77 78 79 80 76 gnd vcc b0 gnd vcc hsync vsync de cap b8 b9 gnd vcc cap gnd vcc b7 vcc b4 b5 b6 b1 b2 b3 gnd 51 55 54 53 52 59 58 57 56 63 62 61 60 67 66 65 64 71 70 69 68 75 74 73 72 g9 cap gnd vcc gn d g7 g8 g4 g5 g6 ma p2 vcc clkout g0 g1 g2 g3 map1 vcc gnd cap vcc mlsb test gnd 27 26 31 30 29 28 35 34 33 32 39 38 37 36 43 42 41 40 47 46 45 44 50 49 48 vcc gnd r7 r8 r9 r5 r6 test2 vcc vcc gnd cap r4 gnd vcc gnd cap oe map0 vcc gnd r0 r1 r2 r3 figure 2. pin diagram THC63LVD1022_rev.1.02_e copyright?2013 thine electronics, inc. 2 thine electronics, inc.
pin description pin name pin # direction type description ra1+, ra1- 2, 1 rb1+, rb1- 4, 3 rc1+, rc1- 6, 5 rd1+, rd1- 10, 9 re1+, re1- 12, 11 lvds 1st link data in. rclk1+,rclk1- 8, 7 lvds clock input for 1st link. ra2+, ra2- 15, 14 rb2+, rb2- 17, 16 rc2+, rc2- 19, 18 rd2+, rd2- 23, 22 re2+, re2- 25, 24 lvds 2nd link data in. rclk2+,rclk2- 21, 20 lvds lvds clock input for 2nd link. test, test2 72, 43 reserved l: normal operation (table. 10) oe 29 output enable h: normal op eration l: fix output signals(hold the previous logic value) mlsb 71 output bit order selection h: msb = 9 / lsb = 0 l: msb = 0 / lsb = 9 map2 ~ 0 62, 55, 30 input lvttl output color mapping selection rch gch bch hhh r g b hhl rbg hlh brg hll b g r lhh g r b lhl g b r llh r g b lll r g b map0:1:2 rgb table 1. pin description THC63LVD1022_rev.1.02_e copyright?2013 thine electronics, inc. 3 thine electronics, inc.
pin description (continued) pin name pin # direction type description de 97 data enable output vsync 96 vsync output hsync 95 hsync output r9 ~ 0 48, 47, 46, 42, 41, 40, 36, 35, 3 4, 33 pixel data output(rch) g9 ~ 0 67, 66, 65, 61, 60, 59, 54, 53, 5 2, 51 pixel data output(gch) b9 ~ 0 92, 91, 90, 86, 85, 84, 81, 80, 7 9, 78 pixel data output(bch) clkout 75 output lvcmos clock output vcc 26, 31, 37, 44, 49, 56, 63, 70, 74, 77, 83, 89, 94, 100 power supply pins gnd 13, 27, 32, 38, 45, 50, 57, 64, 69, 73, 76, 82, 88, 93, 99 ground pins cap 28, 39, 58, 68, 87, 98 - decoupling cap. external 0.1uf or more capacitance required. table 2. pin description THC63LVD1022_rev.1.02_e copyright?2013 thine electronics, inc. 4 thine electronics, inc.
absolute maximum ratings parameter min max unit supply voltage (vcc) -0.3 +4.0 v lvcmos/ttl input voltage -0.3 vcc + 0.3 v lvds input pin -0.3 vcc + 0.3 v junction temperature - +125 c storage temperature -55 +125 c table 3. absolute maximum rating recommended operating conditions symbol parameter min typ max unit - all supply voltage 3.0 3.3 3.6 v ta operating ambient temperature 0 25 +85 c lvds input 20 - 75 - clock frequency lvcmos output 40 - 150 mhz table 4. recommended operating conditions ?absolute maximum ratings? are those valued beyond which the safety of the device can not be guaranteed. they are not meant to imply that the device should be operated at these limits. the tables of ?electrical characteristics? specify conditions for device operation. ?absolute maximum rating? values also include behavior of overshooting and undershooting. equivalent lvds input schematic diagram figure 3. lvds input schematic diagram THC63LVD1022_rev.1.02_e copyright?2013 thine electronics, inc. 5 thine electronics, inc.
power consumption over recommended operating supply and te mperature range unless otherwise specified symbol parameter conditions typ* max unit lvds receiver operating current gray scale pattern (fig.4) rl=100 , c l=5pf, rclk=75mhz 139 - ma i rccw lvds receiver operating current worst case pattern (fig.5) rl=100 , c l=5pf, rclk=75mhz - - ma * typ values are at the conditions of vcc=3.3v and ta = +25oc table 5. power consumption grayscale pattern figure 4. grayscale pattern THC63LVD1022_rev.1.02_e copyright?2013 thine electronics, inc. 6 thine electronics, inc.
worst case pattern rn, gn, bn (n = 09 hsync, vsync de clkout figure 5. worst case pattern electrical characteristics lvcmos/ttl dc specifications over recommended operating supply and te mperature range unless otherwise specified symbol parameter conditions min typ* max unit v ih high level input voltage rs=vcc or gnd 2.0 - vcc v v il low level input voltage rs=vcc or gnd gnd - 0.8 v voh high level output voltage i oh =12ma(data), 16ma(clk) 2.4 - - v vol low level output voltage i oh =12ma(data), 16ma(clk) - - 0.4 v i il input leakage current - - 1 a p d power dissipation - 0.46 - w * typ values are at the conditions of vcc=3.3v and ta = +25oc table 6. lvcmos/ttl dc specifications lvds receiver dc specifications over recommended operating supply and te mperature ra nge unl ess otherwise specified symbol parameter conditions min typ* max unit v ic differential input common voltage 0.6 1.2 1.8 v |v id| differential voltage 100 - 600 mv v th differential input high threshold v ic = 1.2v - - 100 mv v tl differential input low threshold v ic = 1.2v -100 - - mv i inlvds lvds input current - - 20 a *typ values are at the conditions of vcc=3.3v and ta = +25oc table 7. lvds receiver dc specifications THC63LVD1022_rev.1.02_e copyright?2013 thine electronics, inc. 7 thine electronics, inc.
lvcmos/ttl & lvds receiver ac specifications over recommended operating supply and te mperature ra nge unl ess otherwise specified symbol parameter min typ max unit rclk1/2 13.3 - 50 t rcp clk period clkout 6.6 - 25 ns t rch clkout high time 2/7 t rcp 4/7 t rcp 5/7 t rcp ns t rcl clkout low time 5/7 t rcp 3/7 t rcp 2/7 t rcp ns t dout lvcmos data out period 6.6 - 25 ns t rs lvcmos data setup to clkout 2.0 - 4.6 ns t rh lvcmos data hold to clkout 2.0 - 4.6 ns t sk receiver skew margin -400 - 400 ps t rip1 input data position0 - t sk 0 + t sk ns t rip0 input data position1 t rcip /7- t sk t rcip /7 t rcip /7+ t sk ns t rip6 input data position2 2t rcip /7- t sk 2t rcip /7 2t rcip /7+ t sk ns t rip5 input data position3 3t rcip /7- t sk 3t rcip /7 3t rcip /7+ t sk ns t rip4 input data position4 4t rcip /7- t sk 4t rcip /7 4t rcip /7+ t sk ns t rip3 input data position5 5t rcip /7- t sk 5t rcip /7 5t rcip /7+ t sk ns t rip2 input data position6 6t rcip /7- t sk 6t rcip /7 6t rcip /7+ t sk ns t rpll phase lock loop set - - 1 ms * typ values are at the conditions of vcc=3.3v and ta = +25oc table 8. lvcmos/ttl & lvds receiver ac specifications THC63LVD1022_rev.1.02_e copyright?2013 thine electronics, inc. 8 thine electronics, inc.
ac t iming diagrams l vcmos output figure 6. clkout transmission time figure 7. clkout period, high/low time, setup/hold timing THC63LVD1022_rev.1.02_e copyright?2013 thine electronics, inc. 9 thine electronics, inc.
lvds input data position figure 8. lvds input data position phase lock loop set time figure 9. pll lock set time THC63LVD1022_rev.1.02_e copyright?2013 thine electronics, inc. 10 thine electronics, inc.
lvds data timing diagram figure 10. lvds data timing diagram lvds input data mapping (mlsb=high, map[2:0]=high) lvds input data (1 st pixel data) 1 st pix data lvds input data (2 nd pixel data) 2 nd pix data ra10 r4 (n) ra20 r4 (n+1) ra11 r5 (n) ra21 r5 (n+1) ra12 r6 (n) ra22 r6 (n+1) ra13 r7 (n) ra23 r7 (n+1) ra14 r8 (n) ra24 r8 (n+1) ra15 r9 (n) ra25 r9 (n+1) ra16 g4 (n) ra26 g4 (n+1) rb10 g5 (n) rb20 g5 (n+1) rb11 g6 (n) rb21 g6 (n+1) rb12 g7 (n) rb22 g7 (n+1) rb13 g8 (n) rb23 g8 (n+1) rb14 g9 (n) rb24 g9 (n+1) rb15 b4 (n) rb25 b4 (n+1) rb16 b5 (n) rb26 b5 (n+1) rc10 b6 (n) rc20 b6 (n+1) rc11 b7 (n) rc21 b7 (n+1) rc12 b8 (n) rc22 b8 (n+1) rc13 b9 (n) rc23 b9 (n+1) rc14 hsync rc24 - rc15 vsync rc25 - rc16 de rc26 - rd10 r2 (n) rd20 r2 (n+1) rd11 r3 (n) rd21 r3 (n+1) rd12 g2 (n) rd22 g2 (n+1) rd13 g3 (n) rd23 g3 (n+1) rd14 b2 (n) rd24 b2 (n+1) rd15 b3 (n) rd25 b3 (n+1) rd16 - rd26 - re10 r0 (n) re20 r0 (n+1) re11 r1 (n) re21 r1 (n+1) re12 g0 (n) re22 g0 (n+1) re13 g1 (n) re23 g1 (n+1) re14 b0 (n) re24 b0 (n+1) re15 b1 (n) re25 b1 (n+1) re16 - re26 - table 9. lvds input data mapping THC63LVD1022_rev.1.02_e copyright?2013 thine electronics, inc. 11 thine electronics, inc.
output disable mode input signal normal mode setting output disable mode setting oe h l test l h test2 l l map0 x h map1 x h map2 x h other input signals x x table 10. output disable mode setting output signal normal mode output disable mode b9 l other output signals normal operation hi-z table 11. output disable mode signal definition THC63LVD1022_rev.1.02_e copyright?2013 thine electronics, inc. 12 thine electronics, inc.
typical connection figure 11. typical connection diagram THC63LVD1022_rev.1.02_e copyright?2013 thine electronics, inc. 13 thine electronics, inc.
notes 1) cable connection and disconnection do not connect and disconnect the lvds cable, when the power is supplied to the system. 2) gnd connection connect each gnd of the pcb which THC63LVD1022 an d lvds-tx on it. it is better for emi reduction to place gnd cable as close to lvds cable as possible. 3) multi drop connection multi drop connection is not recommended. lvds-tx THC63LVD1022 THC63LVD1022 tclk+ tclk- figure 12. multi drop connection 4) asynchronous use asynchronous using such as following system is not recommended. figure 13. asynchronous use THC63LVD1022_rev.1.02_e copyright?2013 thine electronics, inc. 14 thine electronics, inc.
package figure 14. package diagram THC63LVD1022_rev.1.02_e copyright?2013 thine electronics, inc. 15 thine electronics, inc.
reference of land pattern cy1= h d = e= d= ttyp. = gmin= b= xmax= zmax= zmax/2 14.40 0.370 unit : [mm] 1.15 0.200 16.70 16.000 14.00 17.34 0.500 0.60 figure 15. reference of land pattern the recommendation mounting method of thine device is reflow soldering. the reference pattern is using the calculation result on condition of reflow soldering. notes this land pattern design is a calculated value based on jeita et-7501. please take into consideration in an actual substrate design about enough the ease of mounting, the intensity of connecti on , the density of mounting, and the solder paste used, etc? the optimal land pattern size changes with these parameters. please use the value shown by the land pattern as reference data. THC63LVD1022_rev.1.02_e copyright?2013 thine electronics, inc. 16 thine electronics, inc.
notices and requests 1. the product specifications described in this material are subject to change without prior notice. 2. the circuit diagrams described in this material are examples of the application which may not always apply to the customer's design . we are not responsible for possible errors and omissions in this material. please note if errors or omissions should be foun d in this material, we may not be able to correct them immediately. 3. this material contains our copyright, know-how or other proprietary. copying or disclosing to third parties the contents of this m aterial without our prior permission is prohibited. 4. note that if infringement of any third party's industria l ownership shou ld occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. this product is presumed to be used for general electric equipment, not for the applications which require very high reli abi lity (including medical equipment directly concerning people's life, aerospace equipment, or nuclear control equipment). also, when using this product for the equipment concerned with the control and safety of the transportation means, the traffic signal equipment, or various types of safety equipment, please do it after applying appropriat e measures to the product. 6. despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability , w hich is inevitable to a semi-conduct or product. therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. please note that this product is not designed to be radiation-proof. 8. customers are asked, if required, to j u dge by t h em selves if this product falls under the category of strategic goods under the foreign exchange and foreign trade control law. THC63LVD1022_rev.1.02_e copyright?2013 thine electronics, inc. 17 thine electronics, inc.

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